Processing apparatus typically comprise one or more processing units and a memory. Accesses to the memory may be slower than desired. This may be because there is contention between parallel accesses and/or because the memory storage used has a fundamental limit on its access speed.
A cache memory may intervene between a processing unit and the memory. The cache memory is typically smaller than the memory and may use memory storage that has a faster access speed.
Multiple processing units may be arranged with a cache available for each processing unit. Each processing unit may have its own dedicated cache. Alternatively a shared cache memory unit may comprise separate caches with the allocation of the caches between processing units determined by an integrated crossbar.
It is possible for processing units to read/write the same word. It is therefore important that if a block for a particular memory address is updated in one cache that the blocks for that particular memory address in other caches (should the blocks exist) are also updated or invalidated. The caches have specific circuitry for maintaining coherency between the caches. Therefore, although the caches may be physically or logically separated they are not isolated because of the inter communication required for coherency.